My current circuit:
3clock pulse, with a ~30 sec delay before output. Right now the circuit spends roughly 30 sec in each of (1) and (0) states, and goes like:
0 - 1 - 0 - 1 - 0 - etc
What i need is to have it go through the following chain: 1 - 1 - 0 - 1 - 1 - 0 etc.
So far i have realised that i need to use an AND gate between the clock and the output, however im having issues finding a way to store the signal between clock pulses to avoid 1/0/1 switches and remain with 1/1/0.
One of my ideas involved using a piston to block redstone current during cycles, however due to the fact that cycles are not symmetric, i dont think it will be possible, and instead will end up being 1 -> 1 (blocked 0) -> 1 -> (1 blocked 0) -> 1 etc, since the cycles wont adjust to the blocking.
Any thoughts?